From johnxj at gmx.com Thu Sep 13 19:59:20 2018 From: johnxj at gmx.com (John Jason Jordan) Date: Thu, 13 Sep 2018 10:59:20 -0700 Subject: [ltp] P71, anyone? Message-ID: <20180913105920.726cc209@Devil-Bonobo> I'm considering a Thinkpad P71 and I have some questions: 1) Has anyone put Linux on one? Problems? 2) I'm pretty sure it comes with an M.2 port, but is there also an mSATA port? Or would there be enough space to use an M.2 to mSATA adapter? 3) It comes with USB 3.1 Generation 1 only, including the docking station. Can anyone think of a way to get a Generation 2 connector? From email at andrewnesbit.org Fri Sep 14 02:59:55 2018 From: email at andrewnesbit.org (Andrew Luke Nesbit) Date: Fri, 14 Sep 2018 01:59:55 +0100 Subject: [ltp] P71, anyone? In-Reply-To: <20180913105920.726cc209@Devil-Bonobo> References: <20180913105920.726cc209@Devil-Bonobo> Message-ID: <9ce3d336-91be-8983-e389-e2967a15e013@andrewnesbit.org> Hi John, On 13/09/2018 18:59, John Jason Jordan wrote: > I'm considering a Thinkpad P71 and I have some questions: [...] > 2) I'm pretty sure it comes with an M.2 port, but is there also an > mSATA port? Sometimes M.2 ports can look like mSATA ports. Look in the spec sheet, or even better, a copy of the manual. If it does come with an M.2 port, look to see what the exact form factor is. I made this mistake once when buying a mainboard, i.e., assuming that, just because a spec sheet says "M.2", that it will be usable for an M.2 SSD. When I received the board, I discovered the M.2 port was miniscule. On close reading of the manual I found a footnote that said the M.2 port was 2230 form factor. This means it is only 30 mm in length, which is practically useless for slotting an SSD into. At some point in the past Toshiba made SSD's with the M.2 2230 form factor. They are rare and expensive (although I've seen indications that they are resuming production). > Or would there be enough space to use an M.2 to mSATA adapter? I've been adapters on AliExpress that can convert small M.2 ports into all sorts of other form factors and interfaces, but they are probably more suitable for desktop systems and SFF PC's. Is there a specific reason that you want to go to mSATA? Do you already have an mSATA SSD? Kind regards, Andrew -- OpenPGP key: EB28 0338 28B7 19DA DAB0 B193 D21D 996E 883B E5B9 From sasha.pitosin at mail.ru Wed Sep 26 02:36:12 2018 From: sasha.pitosin at mail.ru (=?UTF-8?B?0KHQsNGI0LAg0J/QuNGC0L7RgdC40L0=?=) Date: Tue, 25 Sep 2018 20:36:12 -0400 Subject: [ltp] getting hdaps up and running on the w530 In-Reply-To: References: <1397149974258-21116.post@n7.nabble.com> <1397209035009-21118.post@n7.nabble.com> <1397230182621-21122.post@n7.nabble.com> <1397452072135-21124.post@n7.nabble.com> <20140414060920.GA29285@dorei.kerker.die-welt.net> <20140414155837.GC29285@dorei.kerker.die-welt.net> Message-ID: <99dd8137-3d71-cb51-45d4-d37f4fc2a61a@mail.ru> On 4/14/14 3:19 PM, Raider Sail wrote: > 1. How do we interface with the APS hardware via the new embedded controller on the W530? Hello, I think I have made some progress with latest ThinkPad accelerometer, observing I/O port communications between the Windows Driver and hardware. Only ports 0x1610 and 0x1611 are used, using an "indirect" addressing mode:  - writing to 0x1610 selects the register to be accessed  - reading (or writing) 0x1611 reads (or writes) the chosen register. It appears that some operations can take a while, and you have to poll register 0x00 until it return zero. Readings are delivered through a FIFO (registers 0x10-0x2f), each entry containing:  - X axis (2 bytes, little-endian)  - Y axis (2 bytes, little-endian)  - One extra byte (maybe related to temperature?) Before accessing the FIFO, 0xff is always written to register 0x01 (latch?), and 0x00 is written to the same register, maybe to release it. Getting new readings involves waiting for the accelerometer to be ready, locking the FIFO, writing 0x11 to register 0x00 and waiting again. Register 0x10 will then contain the number of available FIFO entries (between 0 and 5), followed by the 5-byte records described above in registers 0x11 to (0x11 + 5 * num. of records)-1. Then register 0x2f returns zero and the FIFO can be released. An example of a reading sequence:     0x1610 <-- 0x00     0x1611 --> 0x00 # register 0x00 returns 0x00     0x1610 <-- 0x01     0x1611 <-- 0xff # register 0x01 is written 0xff     0x1610 <-- 0x00     0x1611 <-- 0x11 # register 0x00 is written 0x11     0x1610 <-- 0x00     0x1611 --> 0x11 # register 0x00 returns 0x11 (not ready yet - polling!)     0x1611 --> 0x00 # register 0x00 returns 0x00     0x1610 <-- 0x10     0x1611 --> 0x01 # register 0x10 returns 0x01     0x1610 <-- 0x11     0x1611 --> 0x11 # first data byte     0x1610 <-- 0x12     0x1611 --> 0x02 # second data byte     0x1610 <-- 0x13     0x1611 --> 0x9a # ...     0x1610 <-- 0x14     0x1611 --> 0x02     0x1610 <-- 0x2a     0x1611 --> 0x00     0x1610 <-- 0x2b     0x1611 --> 0x80     0x1610 <-- 0x2f     0x1611 --> 0x00 # register 0x2f returns 0x00     0x1610 <-- 0x01     0x1611 <-- 0x00 # register 0x01 is written 0x00 At boot, the following registers are configured:     0x1610 <-- 0x00     0x1611 --> 0x00 # register 0x00 returns 0x00     0x1610 <-- 0x01     0x1611 <-- 0xff # register 0x01 is written 0xff     0x1610 <-- 0x10     0x1611 <-- 0x81 # register 0x10 is written 0x81     0x1610 <-- 0x00     0x1611 <-- 0x17     0x1610 <-- 0x00     0x1611 --> 0x00     0x1610 <-- 0x10     0x1611 --> 0x01     0x1610 <-- 0x11     0x1611 --> 0x00     0x1610 <-- 0x12     0x1611 --> 0x00     0x1610 <-- 0x13     0x1611 --> 0x00     0x1610 <-- 0x2f     0x1611 --> 0x00     0x1610 <-- 0x01     0x1611 <-- 0x00 # register 0x01 is written 0x00     0x1610 <-- 0x00     0x1611 --> 0x00 # register 0x00 returns 0x00     0x1610 <-- 0x01     0x1611 <-- 0xff # register 0x01 is written 0xff     0x1610 <-- 0x10     0x1611 <-- 0x01 # register 0x10 is written 0x01     0x1610 <-- 0x00     0x1611 <-- 0x14     0x1610 <-- 0x00     0x1611 --> 0x00     0x1610 <-- 0x10     0x1611 --> 0x01     0x1610 <-- 0x2f     0x1611 --> 0x00     0x1610 <-- 0x01     0x1611 <-- 0x00 # register 0x01 is written 0x00     0x1610 <-- 0x00     0x1611 --> 0x00 # register 0x00 returns 0x00     0x1610 <-- 0x01     0x1611 <-- 0xff # register 0x01 is written 0xff     0x1610 <-- 0x10     0x1611 <-- 0xc8 # register 0x10 is written 0xc8     0x1610 <-- 0x11     0x1611 <-- 0x00     0x1610 <-- 0x12     0x1611 <-- 0x02     0x1610 <-- 0x00     0x1611 <-- 0x10 # register 0x00 is written 0x10     0x1610 <-- 0x00     0x1611 --> 0x10 # register 0x00 returns 0x10 (not ready yet - polling!)     0x1611 --> 0x00 # register 0x00 returns 0x00     0x1610 <-- 0x10     0x1611 --> 0xc8     0x1610 <-- 0x2f     0x1611 --> 0x00     0x1610 <-- 0x01     0x1611 <-- 0x00 # register 0x01 is written 0x00 Regards, Sasha