[ltp] T60 power management (fglrx, aticonfig --set-powerstate )

[Florian Manschwetus]

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Nils Kanning wrote:
> On Wed, 2006-08-09 at 10:43 +0200, Florian Manschwetus wrote:
>> Michael Olbrich wrote:
>>> Hi,
>>>
>>> On Tue, Aug 08, 2006 at 10:53:42PM +0200, Nils Kanning wrote:
>>>> how do you do the core disabling? is it a special kernel feature or a
>>>> feature of the centrino_speedstep module?
>>>> which kernel do you use?
>>> echo 0 > /sys/devices/system/cpu/cpu1/online
>>>
>>> michael
>>>
>> at least you can ask tp_smapi how much power you drain from battery
>> (cat /sys/devices/platform/smapi/BAT0/power_now)
>> i could press it down to arround 16 W with wlan
>> (2007 63G)
>> florian
> 
> after doing
> echo 0 > /sys/devices/system/cpu/cpu1/online
> /proc/cpuinfo only shows one cpu. however in /proc/acpi/processor there
> are still both cpus and CPU1/power always shows C1 (this does not depend
> on the state CPU1 was in before disabling it).
> 
> furthermore /sys/devices/platform/smapi/BAT0/power_now does not change
> if i disable the second core. so i do not gain any power.
> 
> here is the output of dmesg (first enabling cpu1):
> SMP alternatives: switching to SMP code
> Booting processor 1/1 eip 3000
> Initializing CPU#1
> Calibrating delay using timer specific routine.. 3657.71 BogoMIPS
> (lpj=7315437)
> CPU: After generic identify, caps: bfe9fbff 00100000 00000000 00000000
> 0000c1a9 00000000 00000000
> CPU: After vendor identify, caps: bfe9fbff 00100000 00000000 00000000
> 0000c1a9 00000000 00000000
> monitor/mwait feature present.
> CPU: L1 I cache: 32K, L1 D cache: 32K
> CPU: L2 cache: 2048K
> CPU: Physical Processor ID: 0
> CPU: Processor Core ID: 1
> CPU: After all inits, caps: bfe9fbff 00100000 00000000 00000140 0000c1a9
> 00000000 00000000
> Intel machine check architecture supported.
> Intel machine check reporting enabled on CPU#1.
> CPU1: Intel Genuine Intel(R) CPU           T2400  @ 1.83GHz stepping 08
> APIC error on CPU1: 00(40)
> 
> (disabling cpu1)
> CPU 1 is now offline
> SMP alternatives: switching to UP code
> 
> nils
> 
> 
so long the cpus are in c3 (with no busmaster you didn't save power) you 
save power because the second core doesn't wake up on activity.
florian

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